1. Field of the Invention
The present invention relates to method and apparatus for interconnecting a semiconductor die or semiconductor device to a carrier substrate. In particular, the present invention relates to a method and apparatus for attaching a semiconductor die face down to a carrier substrate so that the semiconductor die is electrically interconnected to the carrier substrate using both conductive bumps and bond wires.
2. State of the Art
Well known techniques typically used for bonding and electrically connecting a semiconductor die to a substrate, such as a printed circuit board, interposer, or carrier substrate, are flip-chip attachment, wire bonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d). Such techniques are known in the art as Chip-On-Board (xe2x80x9cCOBxe2x80x9d) or, otherwise, Board-On-Chip (xe2x80x9cBOCxe2x80x9d) technology.
Flip-chip attachment generally consists of attaching an active surface of a semiconductor die to a substrate with a plurality of conductive bumps therebetween. Each conductive bump must align and correspond with respective bond pads on the substrate and the semiconductor die to provide electrical interconnection therebetween. The semiconductor die is bonded to the substrate by reflowing the conductive bumps, after which, an underfill material is typically disposed between the semiconductor die and the substrate for environmental protection and to enhance the attachment of the semiconductor die to the substrate.
Although flip-chip packages exhibit excellent response time, from a production standpoint, flip-chip attachment has several challenges due to the numerous amount of conductive bumps necessitated. In particular, if the substrate connection arrangement is not a mirror-image of the conductive bumps on the semiconductor die, electrically connecting the semiconductor die to the substrate is impossible. Such a challenge is exemplified by the methods disclosed in U.S. Pat. Nos. 3,811,186; 4,940,181; 5,477,086; and 5,329,423 for self aligning the conductive bumps.
Turning to the BOC techniques of wire bonding and TAB, the semiconductor die is directly attached to the surface of a substrate, i.e., printed circuit board, interposer, carrier substrate, with an appropriate adhesive, such as an epoxy or adhesive tape. The die may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding. A plurality of bond wires are then discretely attached to each bond pad on the semiconductor die and extend to a corresponding bond pad on the substrate. The bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bondingxe2x80x94using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bondingxe2x80x94using a combination of pressure and elevated temperature to form a weld; and thermosonic bondingxe2x80x94using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. TAB is generally employed to connect ends of metal leads carried on an insulating tape such as a polyimide to respectively attach to the bond pads on the semiconductor die and the bond pads on the printed circuit board. For both wire bonding and TAB techniques, an encapsulant is typically used to cover the bond wires and metal tape leads to prevent contamination.
Among the different methods of wire bonding a semiconductor die to a substrate, one method includes adhesively attaching a semiconductor die to a substrate in the face down orientation. In this orientation, the active surface of the die is adhesively attached to a portion of the substrate, i.e., printed circuit board, interposer, carrier substrate, etc., having one or more wire bonding openings therein so that bond wires can extend through the opening from bond pads on the substrate to bond pads on the active surface of the die. For example, see U.S. Pat. No. 5,719,440, assigned to the assignee of the present invention, disclosing the die adhesively attached face down to a substrate with wire bonding through an opening in the substrate.
This face down semiconductor die orientation is advantageous by allowing shorter wire bonds resulting in less potential for inter-wire contact and shorting. However, problems with this arrangement include moisture becoming trapped in the adhesive between the semiconductor die and substrate, often resulting in the package cracking when the moisture turns to steam as the package is exposed to high temperatures. Other problems include managing the power and ground wire bond interconnections and the difficult routing signals from both an integrity and reliability standpoint, and additionally, the standpoint of meeting the demands of available xe2x80x9creal estatexe2x80x9d. In other words, since the face down semiconductor die orientation is limited to the one or more openings in the substrate which expose the active surface of the semiconductor die for wire bond interconnections, the space on the active surface exposed by the substrate opening severely limits the number of possible interconnections that may be made via the wire bonds. Further, the wire bonds necessitated for the power and ground are larger due to the increased amount of current running therethrough, thus, further compounding the available space problem for each of the wire bond interconnections.
Therefore, in light of the foregoing, it would be advantageous to provide a semiconductor package with increased integrity and reliability as well as better managing the available space for wire bonding in a face down oriented semiconductor die. It would also be advantageous to provide a semiconductor package that substantially prevents trapping moisture therein.
The present invention relates to a semiconductor assembly. The present invention is directed to the interconnections between a semiconductor die attached face down to a carrier substrate.
In a preferred embodiment of the present invention, the semiconductor assembly includes a carrier substrate having a first surface and a second surface with at least one opening in the carrier substrate which extends from the first surface to the second surface. The semiconductor die includes an active surface and a back surface, wherein the semiconductor die is attached face down to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires are attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate.
In one embodiment, the at least one opening is a single opening centrally located in the carrier substrate. The semiconductor die is attached face down over the opening so that centrally located bond pads on the semiconductor die are exposed through the opening and outer bond pads on the die are mirrored with bond pads on the first surface of the carrier substrate with the conductive bumps between such mirrored bond pads. With this arrangement, the plurality of bond wires are attached through the single opening centrally located in the carrier substrate between the centrally located bond pads on the active surface of the semiconductor die and the bond pads on the second surface of the carrier substrate. Therefore, the semiconductor die is electrically interconnected to the carrier substrate by both the conductive bumps and the bond wires.
In a second embodiment, the at least one opening is a plurality of openings located proximate a periphery of the carrier substrate. The semiconductor die is attached face down to the carrier substrate so that peripheral bond pads on the semiconductor die are exposed through the plurality of openings and centrally located bond pads are mirrored with bond pads on the first surface of the carrier substrate with the conductive bumps between such mirrored bond pads. With this arrangement, the plurality of bond wires are attached through the plurality of openings located proximate the periphery of the carrier substrate between the peripheral bond pads on the semiconductor die and the bond pads on the second surface of the carrier substrate. Therefore, in the second embodiment, the semiconductor die is electrically interconnected to the carrier substrate by both the conductive bumps and the bond wires.
According to the present invention, both the conductive bumps and the bond wires share in the electrical interconnection between the semiconductor die and the carrier substrate. In particular, the present invention provides that the conductive bumps include power and ground connections between the semiconductor die and the carrier substrate. Further, the conductive bumps and the plurality of bond wires each collectively include a portion of the signal routing between the semiconductor die and the carrier substrate. By arranging the conductive bumps and the bond wires to share in the electrical interconnection between the semiconductor die and substrate, there is more space on the die for bond pads, and/or, this arrangement allows for a smaller die size.
In the present invention, the semiconductor assembly may include a filler material disposed around the conductive bumps and between the semiconductor die and carrier substrate, which may be applied by injecting, dispensing or flowing the filler material from a dispenser. The semiconductor assembly includes a sealant or encapsulation material to at least encapsulate the plurality of bond wires. The encapsulation material may also substantially encapsulate exposed portions of the semiconductor die. Such encapsulation material may be formed on the semiconductor assembly by a transfer molding process or by a glob top process. In a transfer molding process, the encapsulation material may act as the filler material, depending on the characteristics of the encapsulation material, such as the viscosity.
In the present invention, the conductive bumps are electrical interconnections between the semiconductor die and the carrier substrate. As such, the conductive bumps may comprise any conductive material such as solder balls and/or z-axis conductive material. The conductive bumps may include layers having a core and a shell, in which the core may be a nonconductive polymer. The shell and core may also include conductive polymers, metals, and/or alloys. The conductive bumps may also be in the form of a stud bump or a column.
In another aspect of the present invention, the semiconductor assembly includes interconnect bumps on the second surface of the carrier substrate for electrical interconnection with a printed circuit board. Similar to the conductive bumps, the interconnect bumps may include any conductive material such as solder balls and/or z-axis material. The interconnect bumps may include layers having a core and a shell, in which the core may be a non-conductive polymer. The shell and core may also include conductive polymers, metals, and/or alloys. The interconnect bumps may also be in the form of a stud bump, formed from the wire bonding material, or a column.
In another aspect of the present invention, the semiconductor assembly is mounted to a circuit board in a computer or a computer system. In the computer system, the circuit board is electrically connected to a processor device which electrically communicates with an input device and an output device.
Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings and the appended claims.